Total views : 176

High Performance FIFO Design for Processor through Voltage Scaling Technique

Affiliations

  • Dev Sanskriti Vishwa Vidayalaya, Haridwar, Uttarakhand-249411, India
  • Department of Computer Science, BIAS, Bhimtal, Uttarakhand-263136, India
  • Department of Computer Science, SIT, Pithoragarh, India

Abstract


Green computing is making revolution by bringing high speed processor with less power consumption. Our paper is based on this philosophy. Objectives: To come out High Performance FIFO for processor by minimizing the power consumption. Methods/Statistical Analysis: To make FPGA based design of FIFO we used voltages and frequency scaling techniques. Keeping voltage constant at 2.3 volt we varied frequency from 20MHz to 250MHz and for other experiment we kept the frequency constant and varies voltages from 1volt to 2.3 volt. Findings: The power consumption is reduced to 95.79% on voltage scaling where as there is a 4.38% less power consumption on frequency scaling. Application/Improvements: It will surely help in futuristic processor development.

Keywords

Field Programmable Gate Array (FPGA), First in First Out (FIFO), Hardware Description Language (HDL), High Performance Design, Voltage Scaling.

Full Text:

 |  (PDF views: 185)

References


  • Nunez-Yanez JL. Adaptive voltage scaling with in-situ detectors in commercial FPGAs. Computers, IEEE Transactions on 64. 1 (2015): 45–53.
  • Gupta. T, Verma G, Kaur A, Pandey B, Singh A, Kaur T. Energy Efficient Counter Design Using Voltage Scaling On FPGA. In Communication Systems and Network Technologies (CSNT), 2015 Fifth International Conference on, IEEE. 2015: p. 816–19.
  • Pandey B, Yadav J, Singh YK, Kumar R, Patel S. Energy efficient design and implementation of ALU on 40nm FPGA. In Energy Efficient Technologies for Sustainability (ICEETS), 2013 International Conference on, IEEE. 2013: p. 45–50.
  • Singh S, Kaur A, B. Pandey S. Energy efficient flip flop design using voltage scaling on FPGA. In Power Electronics (IICPE). 2014 IEEE 6th India International Conference on, IEEE. 2014: p. 1–5.
  • Kastensmidt FL, Tonfat J, Both T, Rech P, Wirth G, Reis R, Bruguier F, Benoit P, Torres L, Frost C. Voltage scaling and aging effects on soft error rate in SRAM-based FPGAs. Microelectronics Reliability 54. 9 (2014): 2344–48.
  • Islam SM, Pandey B, Siddiquee SM, Jaiswal S. Simulation of voltage scaling aware mobile battery charge controller sensor on FPGA. In Advanced Materials Research. 893, 2014: p. 798–802.
  • Sharma R, Rohilla L, Oberai A, Pandey S, Sharma V, Kalia K. Voltage Scaling Based Wireless LAN Specific UART Design Based on 90nm FPGA. International Journal of Smart Home. 10(3), 2016.
  • Nunez-Yanez J L. Energy efficient reconfigurable computing with adaptive voltage and logic scaling. ACM SIGARCH Computer Architecture News 42. 4(2014): 87–92.
  • Saxena A, Bhatt A, Pandey B, Tripathi P. HSTL IO standards based processor specific green counter. In International Journal of Control and Automation. 9(7), (2016): p. 331– 42.
  • Pandey B, Md.Rahman, Saxena A, Hussain A, Das B . Leakage Power Reduction with Various IO Standards and Dynamic Voltage Scaling in Vedic Multiplier on Virtex-6 FPGA. In Indian Journal of Science and Technology. 9(25), July 2016.

Refbacks

  • There are currently no refbacks.


Creative Commons License
This work is licensed under a Creative Commons Attribution 3.0 License.