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UART Receiver Synchronization: Investigating the Maximum Tolerable Clock Frequency Deviation


  • Department of Electronics and Communication, Electronics Research and Development Center of India - Institute of Technology, Center for Development of Advanced Computing, Vellayambalam, Trivandrum – 695010, Kerala, India


Objectives: To analyse the maximum tolerable clock frequency deviation in UART receiver for accurate data reception and to derive mathematical expressions for the same. Methods/Analysis: General design techniques and synchronisation problems in UART receivers have been investigated and a mathematical analysis of the designs is done. Various parameters taken into consideration are baud rate, parity/no parity, oversampling ratio and phase difference between transmitter and receiver clocks. Findings: The maximum tolerable frequency deviation, Δmax improves with increasing oversampling ratio at the UART Receiver side. It is also found that the Δmax is independent of the baud rate of operation. Improvements: Improved expressions may be derived by analyzing the effects of clock jitter, rise and fall times of the signals.


Sampling, Serial Communication, Synchronization, UART.

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