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A High Performance Asynchronous Counter using Area and Power Efficient GDI T-Flip Flop
As the technology is increasing day by day in electronic industry, it needs a field which involves packing more and more devices into smaller area. Along with Very Large Scale Integration (VLSI) is a process of integrating much number of devices into a single chip. According to Moore's law the competence of an IC has increased in terms of power, speed and area. Hence the GDI technique is used here, in which many complex logic functions can be designed by using only two transistors. Along side, the memory device plays an important role in digital systems, where the flip flops are the basic building blocks of digital electronic systems. Asynchronous logic in digital system does not use common clock pulse, in place the precious state output will be considered as clock pulse to the next state. Based on the concept of T-flip flop, a new GDI T-Flip flop is designed, which has less number of transistors than other GDI T-flip flops and also, it consumes low power and lesser delay. With this energy efficient GDI T-Flip flop, a high performance Asynchronous down counter is developed in this paper. The comparison is done on the basis of four performance parameters i.e. total Area, delay, Power consumption and power-delay product.
CMOS, Counters, FinFET, GDI, MOSFET, T-Flip Flops.
- Nagendra C, Owens RM, Irwin MJ. Power-delay characteristics of CMOS adders. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 1994; 2(3):377-81.
- Meher P, Mahapatra KK. High speed and low power dynamic logic style. International Journal of VLSI and Embedded Systems. 2013; 2(3):313-7.
- Sharma R, Verma S. Comparitive analysis of static and dynamic CMOS logic design. IEEE International Conference on Computing and Communication Technologies; 2011. p. 231-4.
- Chandrakasan AP, Sheng S, Brodersen RW. Low power CMOS digital design. IEEE J Solid State Circ. 1992; 27(4):473-83.
- Morgenshtein A, Fish, Wagner IA. Gate-diffusion input (GDI) - A novel power efficient method for digital circuits: A detailed methodology. Proc. 14th IEEE Int.ASIC/SOC Conf; 2001. p. 39-43.
- Morgenshtein A, Fish A, Wagner IA. Gate-Diffusion Input (GDI): a power-efficient method for digital combinatorial circuits. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2002; 10(5):566-81.
- Bhole M, Kurude A, Pawar S. (November, 2013). FinFET-benefits, drawbacks and challenges. IJESRT. 2013 Nov; 2(11):3219-22.
- Dangeti M, Singh SN. Minimization of transistors count and power in an embedded system using GDI technique: a realization with digital circuits. Int J Electron Electr Eng. 2012 Sept. 2(9):21-30. ISSN:2277-7040.
- Available from http://en.wikipedia.org/wiki/Flip-flop_(electronics).
- Ziabakhsh S, Zoghi M. Design of a low-power high speed T-flip flop using the Gate-diffusion input technique. 17th Telecommunications forum TELFOR; 2009.
- Available from http://en.wikipedia.org/wiki/Counter.
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