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A High Performance Asynchronous Counter using Area and Power Efficient GDI T-Flip Flop


  • Department of ECE, Sathyabama University, Chennai, India


As the technology is increasing day by day in electronic industry, it needs a field which involves packing more and more devices into smaller area. Along with Very Large Scale Integration (VLSI) is a process of integrating much number of devices into a single chip. According to Moore's law the competence of an IC has increased in terms of power, speed and area. Hence the GDI technique is used here, in which many complex logic functions can be designed by using only two transistors. Along side, the memory device plays an important role in digital systems, where the flip flops are the basic building blocks of digital electronic systems. Asynchronous logic in digital system does not use common clock pulse, in place the precious state output will be considered as clock pulse to the next state. Based on the concept of T-flip flop, a new GDI T-Flip flop is designed, which has less number of transistors than other GDI T-flip flops and also, it consumes low power and lesser delay. With this energy efficient GDI T-Flip flop, a high performance Asynchronous down counter is developed in this paper. The comparison is done on the basis of four performance parameters i.e. total Area, delay, Power consumption and power-delay product.


CMOS, Counters, FinFET, GDI, MOSFET, T-Flip Flops.

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