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A FPGA Implementation of Dual Images based Reversible Data Hiding Technique using LSB Matching with Pipelining
Background: In this digital era, the authentication and proof of ownership has become a vital part in all the multimedia data content like audio, image and video. Data Hiding is one of the familiar methodologies used to authenticate and resolve the issues of copyrights of the digital data. Methods: In this paper the FPGA (Field Programmable Gate Array) implementation of Data Hiding using reversible Dual Image concept is carried out on a gray scale image. Here the FPGA implementation is carried out with and without the concept of pipelining. Findings: In the data hiding process the secret key is embedded in the host image content and analyzed with the values of PSNR (Peak Signal to Noise Ratio) and Embedding capacity. In the last, a comparison for the pipelined and non pipelined mode of data hiding process has been done for the values of area, power and timing. From the results it is noted that the pipelined mode of data hiding gives better result in terms of very less embedding time compared to non pipelined mode with a lesser power consumption. As this data hiding methodology involves only simple operation it is easy to implement as FPGA chip using Verilog HDL Modelling language. Here the entire data hiding operation is carried out by the hardware chip, not by software running on hardware, hence the process of data hiding is fast when compared with all other software implementations. As the whole process of embedding is taking place in real time, we can embed this FPGA data hiding chip as a separate co-processor the data hiding operation with any multimedia device.
Dual Imaging Concept, FPGA based Data Hiding, LSB Bit Matching, Pipelined Embedding, Reversible Data Hiding
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