Total views : 257
A Hybrid Topology for Frequency Divider using PLL Application
In this paper, we present a new type of odd integer divider topology which consume low power and it uses Mod-N counter, DFF and OR gate. In existing methodology divide by 2 topologies involves only D Flip-Flops (DFF), which realized mostly Common Mode Logic DFF (CML) or True Single Phase Clock (TSPC) based DFF. These were high-speed dividers but no flexibility in this topology i.e. it divides the only power of N. So the proposed divider gives more flexibility to the topology like divided by any real odd integer. While designing a new topology the limitations are operating frequency range, a number of transistor and power consumption. Based on this consideration the 3T NAND and TSPC based Flip-Flop are investigated. The maximum operating frequency of the TSPC divide by 2 is reaches at 2.4 GHz with 1.1931 mw power consumption and is 50% low power consumption compared to the NAND_DFF based frequency divider. Similarly, divide by 3, divide by 5 and divide by 7 also consume low power with less number of transistor compare to the NAND_DFF based frequency divider. So the results show the TSPC is DFF’s more preferable for PLL application and RFIC. The TSPC_DFF based frequency divider designed using 0.18 um CMOS process technology.
Frequency Divider, Low Power, Mod-N Counter, PLL, TSCP DFF, 3T NAND Gate.
- Manthena VK, Do MA, Yeo KS, Boon CC, Lim WM. A low-power single-phase clock multiband flexible divider. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2012 Feb; 20(2):376–80.
- Farsiani S, Sahafi A, Sobhi J. A novel topology for modular frequency dividers with enhanced speed and power efficiency. Springer Science+Business Media New York. 2015; 84(2):161–71.
- Manthena VK, Do MA, Yeo KS, Boon CC, Lim WM. Design and analysis of ultra low power true single phase clock CMOS 2/3 Prescaler. IEEE Transactions on Circuits and Systems - I: Regular Papers. 2010 Jan; 57(1):72–82.
- Priya MG, Baskaran K, Srinivasan S. Robust and energy efficient universal gates for high-performance computer networks at 22 nm process technology. International Journal of Computer, Electrical, Automation, Control and Information Engineering. 2013; 7(11):1501–6.
- Razavi B. Challenges in the design of frequency synthesizers for wireless applications. Integrated Circuits and Systems Laboratory; Los Angeles: University of California; 1997. p. 1–8.
- Chen WH. High-speed low-power true single-phase clock. IEEE Transactions on Circuits and Systems - Ii: Express Briefs. 2011 Mar; 58(3):144–8.
- Joshi H, Ranjan SM, Nath V. Design of High-Speed Flip-Flop based frequency divider for GHz PLL System: Theory and Design Techniques in 250 nm CMOS Technology. International Journal of Electronics and Computer Science Engineering. 2012; 1(3):1220–6.
- Shafi A, Sobhi J, Sahafi M, Farhanieh O. An ultra low power frequency divider for 2.4 GHz ZigBee frequency synthesizer. 7th International Conference on Electrical and Electronics Engineering; Bursa, Turkey. 2011 Dec. p. 214–6.
- Jasmin M. Design of novel low power dual edge triggered Flip-Flop. Indian Journal of Science and Technology. 2015 Nov; 8(32):1–7.
- Verma G, Kumar M, Khare V. Low power techniques for digital system design. Indian Journal of Science and Technology. 2015 Aug; 8(17):1–6.
- There are currently no refbacks.
This work is licensed under a Creative Commons Attribution 3.0 License.