Total views : 139

TCAD Simulation and Analysis of Drain Current and Threshold Voltage in Single Fin and Multi-Fin FinFET

Affiliations

  • Department of Electonics Engineering, G.H. Raisoni College of Engineering, RTMNU University, Chhatrapati Shivaji Maharaj Administrative Premises, Ravindranath Tagore Marg, Nagpur - 440001, Maharashtra, India

Abstract


Objectives: This study involves analysis the characteristics of Tri-gate single and double-fin FinFET. It shows the threshold voltage change due to depletion charges. Further, we investigate the effect of increasing number of fins on drain on-off current Methods/Statistical Analysis: In this work, it characterize leakiest path (minimum potential point in the channel) at weak inversion and strong inversion using analytical model. Here, the drain current equation is modelled by considering the effects of the depletion charges in the channel near the Source/Drain and substrate interface. Later, these results are verified using TCAD simulations. Findings: This model is extended for multi-fin FinFET, for analyzing the effect of increasing the number of fins and varying the thickness of fin on the drain ON (at VGS=VDD) current and drain OFF (at VGS=0) current (Leakage current) of trigateFinFET. Finally, it analyze the corner effect in trigateFinFET and propose a solution to reduce it. Application/Improvement: The increase in Threshold voltage with the inclusion of depletion charges. Also, an order increase in drain ON current with two fins keeping the short channel effects minimized.

Keywords

Corner Effect, Drain Current, FinFET, Round Corner

Full Text:

 |  (PDF views: 125)

References


  • Moore G. Cramming more components onto integrated circuits, Reprinted from Electronics, volume 38, number 8, April 19, 1965, pp.114 ff. IEEE Solid-State Circuits Newsl. 2006;20(3):33-35.
  • Roy K, Mukhopadhyay S, Mahmoodi-Meimand H. Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits. Proceedings of the IEEE. 2003;91(2):305-327.
  • Colinge J. Silicon-on-insulator technology. Boston: Kluwer Academic Publishers; 1991.
  • Chenming Hu, Bokor J, Tsu-Jae King, Anderson E, Kuo C, Asano K et al. FinFET-a self-aligned double-gate MOSFET scalable to 20 nm. IEEE Trans Electron Devices. 2000;47(12):2320-2325.
  • Singhal S, Kumar S, Upadhyay S, Nagaria RK. Comparative study of Double Gate SOI FinFET and trigate Bulk MOSFET structures. 2013 Students Conference on Engineering and Systems (SCES). 2013; 1- 5.
  • Bhattacharya D, Jha NK. FinFETs: from devices to architectures. Digitally-Assisted Analog and Analog-Assisted Digital IC Design. :21–55.
  • Tang X, De V, Meindl J. Intrinsic MOSFET parameter fluctuations due to random dopant placement. IEEE Transactions on Very Large Scale Integration (VLSI) Systems IEEE Trans VLSI Syst. 1997;5(4):369–76.
  • Fasarakis N, Tsormpatzoglou A, Tassis DH, Pappas I, Papathanasiou K, Bucher M, et al. Compact Model of Drain Current in Short-Channel Triple-Gate FinFETs. IEEE Trans Electron Devices IEEE Transactions on Electron Devices. 2012;59(7):1891–8.
  • Colinge J-P. FinFETs and other multi-gate transistors. New York: Springer; 2008.
  • Papathanasiou K, Theodorou C, Tsormpatzoglou A, Tassis D, Dimitriadis C, Bucher M, et al. Symmetrical unified compact model of short-channel double-gate MOSFETs. Solid-State Electronics. 2012;69:55–61.
  • Fasarakis N, Tsormpatzoglou A, Tassis DH, Pappas I, Papathanasiou K, Bucher M, et al. Compact Model of Drain Current in Short-Channel Triple-Gate FinFETs. IEEE Trans Electron Devices IEEE Transactions on Electron Devices. 2012;59(7):1891–8.
  • Fasarakis N, Tsormpatzoglou A, Tassis D, Dimitriadis C, Papathanasiou K, Jomaah J, et al. Analytical unified threshold voltage model of short-channel FinFETs and implementation. Solid-State Electronics. 2011;64(1):34–41.
  • Suzuki K, Tosaka Y, Sugii T. Analytical threshold voltage model for short channel n/sup /-p/sup / double-gate SOI MOSFETs. 1995 IEEE International SOI Conference Proceedings. 1996;43(5):732-8
  • Baldauf T, Wei A, Herrmann T, Flachowsky S, Illgen R, Hontschel J, et al. Suppression of the corner effects in a 22 nm hybrid Tri-Gate/planar process. 2011 Semiconductor Conference Dresden. 2011.
  • Fossum J, Yang J-W, Trivedi V. Suppression of corner effects in triple-gate MOSFETs. IEEE Electron Device Lett IEEE Electron Device Letters. 2003;24(12):745–7.
  • Sun WYang D. The corner rounding modeling technique in SPICE simulations for deeply scaled MOSFETs. Journal of Semiconductors. 2013;34(11):114008.

Refbacks

  • There are currently no refbacks.


Creative Commons License
This work is licensed under a Creative Commons Attribution 3.0 License.