Indian Journal of Science and Technology
Year: 2015, Volume: 8, Issue: 22, Pages: 1-6
S. Anusha1* , T. R. Shanmugapriya1 , S. Venkatalakshmi 1 ,Har Narayan Upadhyay2 and V. Elamaran2
1 Department of Electronics and Communication Engineering, School of EEE, SASTRA University, Thanjavur - 613401, Tamil Nadu, India; [email protected], [email protected], [email protected]
2 Department of ECE, School of EEE, SASTRA University, Thanjavur - 613401, Tamil Nadu, India; [email protected], [email protected]
In the current semiconductor technology evolution, there is a huge demand in designing a low power, high speed adders with less area. As adders are essential components in the data-path of any computer system, adder modules are needed to be enhanced for better performance. One such efficient adder implementation is the Carry Look-Ahead Adder (CLA) which is designed to overcome the latency introduced by rippling effect of carry bits in a conventional Ripple Carry Adder (RCA). Further, the use of this CLA module in the place of Ripple Carry Adder module inside a Carry Select Adder (CSEA) is proposed for increased speed. Also, a novel implementation of adder, making use of the fact that the sum and carry are compliment of one another, except when all the inputs are same is presented. Simulation results show that a 4-bit carry select adder provides a better performance at the cost of power dissipation as 89.211 μW compared with 38.414 μW by a ripple carry adder with 0.12 μm technology processes. In this study, these high speed adders are implemented with the help of the Digital Schematic (DSCH) software tool, Micro wind layout editor tool and Quartus II synthesis software tool. This Quartus II synthesis tool is used for the implementation of adders on Altera EP2C20F484C7 FPGA device. These kinds of adders are further to be extended to build high-speed multipliers which are most important for the applications like digital signal processors, microprocessors, etc.
Keywords: Altera FPGA, Carry Look-Ahead Adders, High Speed Adders, Reduced Full Adder, VLSI
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