• P-ISSN 0974-6846 E-ISSN 0974-5645

Indian Journal of Science and Technology


Indian Journal of Science and Technology

Year: 2016, Volume: 9, Issue: 29, Pages: 1-6

Original Article

A Hybrid Topology for Frequency Divider using PLL Application


In this paper, we present a new type of odd integer divider topology which consume low power and it uses Mod-N counter, DFF and OR gate. In existing methodology divide by 2 topologies involves only D Flip-Flops (DFF), which realized mostly Common Mode Logic DFF (CML) or True Single Phase Clock (TSPC) based DFF. These were high-speed dividers but no ­flexibility in this topology i.e. it divides the only power of N. So the proposed divider gives more flexibility to the ­topology like divided by any real odd integer. While designing a new topology the limitations are operating frequency range, a number of transistor and power consumption. Based on this consideration the 3T NAND and TSPC based Flip-Flop are investigated. The maximum operating frequency of the TSPC divide by 2 is reaches at 2.4 GHz with 1.1931 mw power consumption and is 50% low power consumption compared to the NAND_DFF based frequency divider. Similarly, divide by 3, divide by 5 and divide by 7 also consume low power with less number of transistor compare to the NAND_DFF based frequency divider. So the results show the TSPC is DFF’s more preferable for PLL application and RFIC. The TSPC_DFF based frequency divider designed using 0.18 um CMOS process technology.
Keywords: Frequency Divider, Low Power, Mod-N Counter, PLL, TSCP DFF, 3T NAND Gate 


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