A Study on Advanced High Speed and Ultra Low Power ADC Architectures

Anil Khatak; Sanjeev Dhull  and Manoj Kumar Taleja

doi:10.17485/ijst/2017/v10i10/86067

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A Study on Advanced High Speed and Ultra Low Power ADC Architectures

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Indian Journal of Science and Technology

DOI: 10.17485/ijst/2017/v10i10/86067

Year: -0001, Volume: 10, Issue: 10, Pages: 1-8

Original Article

A Study on Advanced High Speed and Ultra Low Power ADC Architectures

Anil Khatak¹, Sanjeev Dhull² and Manoj Kumar Taleja³

*Author for correspondence
Mohammad Hayati
Department of Mining, Faculty of Engineering, Lorestan University, Khorramabad, Iran; Email: [email protected]

This work is licensed under a Creative Commons Attribution 4.0 International License.

Abstract

Background: Analog-to-digital converter (acronym as ADC) is an electronics device used to convert a continuous physical signal to a digital number. Over recent years, different advancement has been done and both the beginner as well as expert can be bewildered to differentiate their limitations and benefits. Objective: To overcome this problem this paper provides a brief study about these advance architectures and their parameters. The deliberation of these parameters can make a suitable decision to adopt a better architecture for the purpose of research. Methods: reviewed in this paper include parametric and non parametric ultra low, high speed, low noise architectures.

Keywords: ADC Architectures, SAR DAC, TI ADC, PWM ADC