• P-ISSN 0974-6846 E-ISSN 0974-5645

Indian Journal of Science and Technology


Indian Journal of Science and Technology

Year: 2016, Volume: 9, Issue: 17, Pages: 1-7

Original Article

Analysis of Low Power Conditional Sum Adder


Objective: To implement high speed arithmetic systems especially conditional sum adder is used. It consists mainly conditional cells and sum cells. Method/Analysis: It contains sum and carry with input 1 and 0. These are used to reduce delay generated by the carry propagator. The advantage using conditional sum adder is addition is much faster. Finding: In this project we are going to deal with the low power conditional sum addition rule. By doing this it will basically reduce the nodes which are present internally and number of multiplexer in the adder design. By implementing this adder in cadence software the power will be reduced and the process can be done by applying clock gating and by without applying clock gating. Novelty/Improvement: For implementing this adder Verilog code is used. And this will be executed in cadence software. Because of using Verilog code, using the digital cadence software.

Keywords: Conditional Carry Addition (CCA), Clock Gating, Conditional Sum Adder (CSA), Low Power


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