Indian Journal of Science and Technology
Year: 2018, Volume: 11, Issue: 17, Pages: 1-5
V. Jamuna* , P. Gomathi and A. Arun
Electronics and Communication Engineering, M. Kumarasamy College of Engineering, Karur, Thalavapalayam – 639113, Tamil Nadu, India; [email protected], [email protected], [email protected]
*Author for correspondence
Electronics and Communication Engineering, M. Kumarasamy College of Engineering, Karur, Thalavapalayam – 639113, Tamil Nadu, India; [email protected]
Objectives: FIR filter structure is designed with area and delay optimization is designed using Systolic Architecture and Associativity High Level Transformation technique in this paper. Finite Impulse Response (FIR) filter structure with optimized parameters is one of the major challenges in VLSI Signal Processing. Methods/Statistical Analysis: The designed FIR filter is designed using Modelsim for functionality verification and the structure is implemented in Spartan 3E FPGA kit using Xilinx ISE simulator for the analysis of the designed architecture. Findings: The FIR filter is designed with 4-Tap, 8-Tap and 16-Tap length and the designed architecture using Systolic architecture with Associativity technique shows 8.9%, 2.3% and 2.4% reduction in LUT for 4-Tap,8-Tap and 16-Tap filter respectively and 14.22%,11.89% and 12.32% reduction in delay for 4-Tap,8-Tap and 16-Tap filter respectively. Application/Improvements: Further Associativity techniques may be used for future work.
Keywords: Architecture, FIR Filter, High Level Transformation
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