Indian Journal of Science and Technology
Year: 2016, Volume: 9, Issue: 47, Pages: 1-5
V. Jean Shilpa1*, P. K. Jawahar1 and S. Karthik2
*Author for correspondence
V. Jean Shilpa
Department of ECE, B.S. Abdur Rahman University, Chennai - 600048, Tamil Nadu, India; [email protected]
Objectives: A hardware-software co-design of Least Mean Square (LMS) adaptive FIR filter utilized for the real time noise cancellation purpose has been designed and demonstrated. Method/Analysis: This LMS adaptive filter which serves as a better choice in filtering real-time signals with noise, is being designed as an IP for various different users to make the filter reconfigurable to their designs. Fascinating feature about creating an IP on Zedboard which belong to the Zynq series of FPGA boards is to design the LMS filter in Simulink and convert to RTL (Register Transfer Level) logic by employing HDL coder. This process simplifies the task of either writing an HDL code or designing circuits using transistors, which is time-consuming and cumbersome. Findings: To estimate the performance the IP designed is profiled with the Simulink of MATLAB to estimate the functions, which takes more time for execution in the Simulink design of LMS adaptive filter. Profiling the application, it has been found out that LMS algorithm block for the calculation of adaptive coefficients takes around 311.63ns time/call of the execution time. Hence only this block is imported to FPGA as a soft-core block and interconnected with the hardcore ARM cortex A9 processor block which achieves hardware-software co-design of LMS adaptive filter. Application: This method simplifies the process of hardware-software co-design process, which can be applied to any complex design that can be generated from MATLAB/Simulink and generate the same design as an application to run on an advanced FPGA board.
Keywords: Field Programmable Gate Array (FPGA), IP (Intellectual Property), LMS (Least Mean Square) Algorithm, Simulink, ZedBoard (Zynq Evaluation and Development Board)
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