Indian Journal of Science and Technology
Year: 2013, Volume: 6, Issue: 5, Pages: 1-9
Subha Sri Thirveedhi1* and Muthaiah Rajappa2
1 PG Student, School of Computing (VLSI),[email protected]1
2 Professor, School of Computing (VLSI), [email protected]2
*Author For Correspondence
Subha Sri Thirveedhi
PG Student, School of Computing (VLSI)
Email: [email protected]
In processing the real world data Digital Signal Processing algorithms provide unbeatable performance. One of the DSP algorithms is COordinate Rotation DIgital Computer (CORDIC). For real-time airborne computation, CORDIC act as a special purpose digital computer. Basically the CORDIC is categorized in two different styles such as sequential (folded) and combinational (unfolded). This paper presents a novel architecture of CORDIC using redundant arithmetic i.e., RA-CORDIC. The RA-CORDIC structure shows better latency and obtains maximum throughput. The structure has been coded in VERILOG, synthesis analysis are performed using Xilinx ISim tool and targeted on Xilinx FPGA synthesis tool.
Keywords: FPGA, CORDIC Algorithm, Folded & Unfolded Architectures, Redundant Arithmetic.
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