Indian Journal of Science and Technology

Abstract

Background: Auditory Compensation is the primary block of the hearing aid to compensate the loss in the hearing. The amount of amplification required for a patient is provided by the audiologist in the audiogram. Audiogram is a graph indicating the loss in hearing with respect to frequency. Most of the hearing aids available in the market are developed using filter bank method to divide the signal into various bands and then amplify the signal. Key aspects while designing the auditory compensation block are power dissipation, group delay by the filters, signal attenuation and reconstructing the signal. Objectives: The work here targets to design and develop a novel algorithm for low power implementation of auditory compensation block with the help of Short Time Fourier Transform (STFT). Methods: The algorithm is employed to determine the frequency range of audio signal using STFT which is to be selectively amplified as per the audiogram. Verilog language is used to implement the design. The complete ASIC flow up to generation of Graphic Data System (GDSII) files is carried out. Findings: The algorithm implements the auditory compensation block of the hearing aid successfully with low power consumption and increasing the intelligibility of the speech by solving issues present in the existing filter bank approach. Novelty: Presently Filter banks are used to perform auditory compensation; the work carried out is using STFT which is the novelty of the work.

Keywords: Hearing loss; hearing aid; audiogram; auditory compensation; STFT