Indian Journal of Science and Technology

Abstract

Objectives: This study proposes an optimized power-efficient cryptosystem that is suitable for Wireless Sensor Networks. Methods: A number of cryptographic algorithms have been proposed to secure Wireless Sensor Networks. However, these compute-intensive and power-hungry algorithms do not take into consideration the limitations of resource found on the sensor nodes. We propose profiling some of these popular algorithms to identify the speed bottlenecks and develop hardware accelerators that maintain the real-time performance, with an efficient use of power. Findings: The proposed optimizations to the hardware accelerators were mapped to reconfigurable computing devices. Results show that the performance of the proposed hardware outperforms the software implementation running on contemporary CPU by up to 21.9×. In addition, the results indicate that the hardware is efficiently managing its power budget. Application: These accelerators can be utilized in heterogeneous system architectures, where the CPU controls the overall operations, and the accelerators efficiently perform the necessary encryption and decryption.
Keywords: Cryptography, FPGA, Power Efficiency, Reconfigurable Computing, WSN