Indian Journal of Science and Technology
DOI: 10.17485/ijst/2009/v2i10.14
Year: 2009, Volume: 2, Issue: 10, Pages: 41-43
Original Article
G.M. Bhat*, M. Mustafa**, Shabir Ahmad** and Javaid Ahmad**
*University Science Instrumentation Center, University of Kashmir, Srinagar, India
**Post Graduate Department of Electronics and Instrumentation Technology, University of Kashmir, Srinagar, India
*Author for the correspondence:
Shabir Ahmad
Post Graduate Department of Electronics and Instrumentation Technology,
University of Kashmir, Srinagar, India
E-mail: [email protected]
VHDL modeling and simulation of a typical data scrambler and descrambler for secure data communication has been presented. The encoder and decoder has been implemented using VHDL approach which allows the reconfigurablity of the proposed system such that the key can be changed as per the security requirements. The power consumption and space requirement is very less compared to conventional discrete I.C. design which is pre-requisite for any system designer. The design has been synthesized on EP1S0F484C5 of Straitx FPGA family. The results of the simulation have been found to be satisfactory and are in conformity with theoretical observations.
Keywords: Scrambler, Descrambler, VHDL, and FPGA.
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