Indian Journal of Science and Technology

Abstract

Wave Pipelining has been used in order to reduce the area without degrading its performance and also to improve the speed. In pipelining the throughput is achieved with the compensation of area and the critical path will be same as the original architecture. While considering of larger circuits the area places an important role where the cost is a major issue. Hence in order to reduce the area the latches are removed which produces the technique of wave pipelining. The concept of Wave Pipelining optimize the area and speed when compared to the pipelining architectures. Thus the Wave Pipelining is applied in the FFT architecture for achieving less area. The FFT pipelined architecture is based on splitting the architecture by stages. Each stage is evaluated with effective structure. It’s noted that by using the internal clock which increases both speed and reduces clock loads the number of gates used in the pipelined structure is reduced in using wave pipelining. The Wave Pipelining technique have to be implemented in a 32-bit FFT Pipelined architecture which is suitable for a digital signal processing applications for image processing and for conversion of frequency domain to time domain. And to compare the area and speed of the WP architecture and pipelined architecture.
Keywords: DIF, DIT, Multiplier, Pipelining, 32-bit FFT Processor, Wave Pipelining (WP)