The trend towards lowpower IC design is driven by the increasing demand for longlife portable devices. Carry lookahead adder (CLA), carry skip/bypass adder, conditional sum adder, carry select adder (CSLA), parallel prefix and other adder architectures have been proposed to mitigate rippling of carry in ripple carry adder (RCA). CSLA need less time to provide the carry output
In adiabatic logic (AL) circuits during switching, the charge is recycled in form of trapezoidal voltage (clock)
The losses incurred in adiabatic circuits are discussed in
A N+1bit BEC is used instead of the Nbit RCA in the modified architecture to decrease area and power consumption
Adder is one of the most essential blocks needed to implement any arithmetic circuitry. The power consumption is very critical issue in any adder circuits along with the speed. Many adders were proposed in literature, but still consume more power. The literature provides conclusive results that adiabatic logic helps in realizing lowpower circuits (IPGL). Hence, adders can be designed for highspeed operation with lowpower consumption incorporating adiabatic logic. Thus, the aim of this study is to propose a modified square root CSLA with AOC and BEC in adiabatic logic (IPGL) which can be used for high speed and less power applications.
The rest of this paper is organized as follows: Design methodology of CMOS and adiabatic adders are discussed in Section 2. Section 3 presents the obtained results in terms of power and delay, and finally conclusions derived with future scope in Section 4.
The circuits are designed and simulated using Cadence Virtuoso on CMOS 180 nm technology at V_{DD }= 1.8 V. Since PMOS is slower than NMOS, they have different rise and fall times. CMOS circuits to have symmetrical rise and fall times, sizing of the transistors is very important. DC analysis of static CMOS inverter is performed. Based on DC analysis, a transistor sizing (r) of 2.75 is used for the circuits. Lengths of both the MOS transistors were kept the same. CSLA can be constructed using RCAs and BECs. to decrease the area occupied by the CSLA, a Binary to Excess1 Converter (BEC) can be considered instead of an RCA. A N+1bit BEC is used instead of the Nbit RCA in the modified architecture to decrease area and power consumption
A 1bit CMOS full adder is realized and cascaded to obtain 16bit adder. The Cadence Virtuoso implementation of the static CMOS based 16bit linear CSLA is as depicted in
The linear CSLA may produce wrong outputs initially because of miss match in delays. As first stage carry output (MUX) come one cycle later than the inputs of second stage. To overcome miss match in the delay at each stage, the SCSLA architecture is used
PFAL doesn’t produce correct outputs at high frequencies. This can be overcome using IPGL
The modified addone scheme discussed in
The simulation results of the adder circuits are presented in this section. We first compared the performance of different adiabatic families with respect to the number of transistor, power consumed, and operating frequency of an inverter. Delay analysis is then performed for different adder s. This was followed by performing a power analysis. Finally, calculations regarding the power saving factor were analyzed using Cadence Virtuoso and Spectre.
The IPGL based circuits operate at higher frequencies when compared to ECRL and PFAL. To illustrate, CMOS inverter is designed and simulated in static CMOS and in other AL circuits at 20 MHz, with load capacitance (C_{L}) of 10 pF, at V_{DD} of 1.8 V. Power consumption values of different adiabatic inverters are shown in
Sl. No. 
Frequency (MHz) 
Power consumed by static CMOS based RCA (mW) 

4bit 
8bit 
16bit 

1. 
30 
0.078 
0.173 
3.376 
2. 
100 
0.258 
0.535 
3.937 
3. 
400 
1.028 
2.14 
5.151 
4. 
800 
2.018 
3.507 
5.847 
5. 
1000 
2.38 
4.561 
24.91 
From
Sl. No. 16bit CMOS based Architectures Power Consumed (µW) 1. Linear CSLA with RCA 29.87 2. SCSLA with RCA 32.56 3. SCSLA with BEC 22.33
The power consumed by 16bit SCSLA at various frequencies is depicted in
Sl. No. 
Frequency (MHz) 
Power consumed (mW) 

Static CMOS 
IPGL 

1. 
30 
1.772 
0.743 
2. 
100 
4.074 
1.909 
3. 
500 
15.150 
4.970 
4. 
800 
19.490 
6.137 
5. 
1000 
24.910 
7.948 
Sl. No. 
16bit Adder Architectures 
Transistor count when realized using 

Static CMOS 
IPGL 

1. 
Linear CSLA with RCA 
940 
1306 
2. 
SCSLA with RCA 
1028 
1502 
3. 
SCSLA with BEC 
844 
1280 
4. 
SCSLA with AOC 
820 
1016 
IPGL based 16bit SCSLA realized using AOC requires 21.72% lesser area when compared to IPGL based 16bit SCSLA realized with BEC and 32.36% lesser area when compared to IPGL based 16bit SCSLA realized with RCA. Hence, AOC based IPGL is preferred over both RCA and BEC in design of SCSLA.
A 16bit static CMOS based SCSLA realized with RCA and BEC is compared with
Power analysis of SCSLA in CMOS logic and IPGL with BEC and AOC for various frequencies is depicted in
CMOS Adder Architectures 
Power Consumed 


Proposed 

16bit SCSLA with RCA 
30.567 mW 
32.56 µW 
16bit SCSLA with BEC 
25.79 mW 
22.33 µW 
16bit SCSLA Architectures 
Power consumed (mW) 
Static CMOS based with AOC 
9.73 
IPGL based with AOC 
1.022 
At 1 GHz, the power consumed by the AOC based circuit is nearly 60% lesser than the BEC circuit in IPGL. Hence, IPGL based 16bit SCSLA with AOC is the preferred circuit in high frequency of operation for low power applications.
Improvement in power saving can be analysed for IPGL based adder over static CMOS adder using power saving factor (PSF). PSF is defined as power consumed by a static CMOS circuit divided by the power consumed by the same circuit implemented in any adiabatic logic.
Power saving factor can be calculated using the Equation (2).
The PSF obtained by realizing a square root CSLA with BEC in both CMOS and IPGL is shown in
Hence, IPGL based (adiabatic) designs are preferred in low power and high frequency applications. The power consumption increases linearly for higher order bits. The proposed AOC removes the area overhead of SCSLA by replacing one of the RCA or BEC and also outperforms the SCSLAs in both area and power consumption.
In this study, a comparative analysis between linear and square root carry select adder is presented. Highspeed and low power SCSLA with BEC and AOC is realized in IPGL and in static CMOS logic. SCSLA reduced the delay by 80% when compared to a ripple carry adder. The IPGL based SCSLA realized with BEC consumed almost 60% lesser power compared to CMOS based logic. At 1 GHz operating frequency, results inferred a PSF of 3.134 using IPGL based SCSLA realized with BEC. At 1 GHz the proposed IPGL based 16bit SCSLA with AOC consumed 87 % lesser power when compared to the static CMOS based adder. A PSF of 8.241