A low-leakage current power 45-nm CMOS SRAM

A low leakage power, 45-nm 1Kb SRAM was fabricated. The stand-by leakage power of a 1K-bit memory cell array incorporating a newly-developed leakage current reduction circuit called a self-controllable voltage level (SVL) circuit was only 3.7 nW, which is 5.4% that of an equivalent conventional memory-cell array at a VDD of 1.8V. On the other hand, the speed remained almost constant with a minimal overhead in terms of the memory cell array area.


Introduction
Battery-driven portable systems need low leakage power techniques. There are 2 well-known techniques that reduce leakage power (P ST ). One is to use a multithreshold-voltage CMOS (MTCMOS) (Mutoh et al., 2008). It effectively reduces PST by disconnecting the power supply through the use of high V t MOSFET switches. However, there are serious drawbacks with the use of this technique, such as the fact that both memories and flipflops based on this technique cannot retain data. The other technique involves using a variable thresholdvoltage CMOS (VTCMOS) (Kuroda et al., 2009) that reduces P ST by increasing the substrate-biases. This technique also faces some serious problems, such as a large area penalty and a large power penalty due to the substrate-bias supply circuits. To solve the abovementioned drawbacks, a small leakage current reduction circuit called a self-controllable voltage level (SVL) circuit has been developed that not only significantly decreases PST, but also retains data during a stand-by period. We applied this technique to a 1K-bit 45nm SRAM that could potentially be used in future multimedia mobile applications to examine the effects of the SVL circuit on the P ST of storage circuits. Circuit design, fabrication and characteristics

Self-controllable voltage level (SVL) circuit
The SVL circuit consists of an upper SVL (U-SVL) circuit and a lower SVL (L-SVL) circuit ( Fig. 1), Where a single inverter has been used as the load circuit. The SVL circuit shown in Fig. 2 is applied to the SRAM memory cell array. The U-SVL circuit is constructed of a wide channel pull-up pMOSFET switch (pSW) and multiple nMOSFET resistors (nRSm; m=1, 2, •••) connected in series. Similarly, the L-SVL circuit incorporates a wide channel pull-down nMOSFET switch (nSW) and multiple series-connected pMOSFET resistors (pRSm). While the load circuit is active (i.e., CLB="0" and CL="1"), both the pSW and nSW are turned on, but the nRS1 and pRS1 are turned off. Therefore, the U-SVL and L-SVL circuits can supply a maximum supply voltage V D (=V DD ) and a minimum ground-level voltage V S (=V SS =0), respectively, to the active load circuit. Thus, the operating speed of the load circuit can be maximized.
When the load circuit is in stand-by (i.e., CLB="1" and CL="0"), all the nRSm and pRSm switches are turned on, and both the pSW and nSW are turned off. Thus, the U-SVL and L-SVL circuits respectively generate a slightly lower supply voltage V D (=V DD-vn <V DD ) and a relatively higher "ground-level" voltage V S (=VP>0V), where v n and v p are the total voltage drops of all nRSm and all pRSm, respectively. Thus, the back-gate biases (V BG s) {i.e., source voltages (V s )} of both the "cut-off" pMOSFETs and then MOSFETs in the stand-by load circuit are increased and are given by v n and -v p , respectively. The increase in V BG s will increase the V t s of the "cut-off" MOSFETs. Therefore, the leakage currents of the "cut-off" MOSFETs decrease. Furthermore, the increase in V s increases the "write" operating margin (Mizuno & Nagano, 2010). Similarly, the V ds s of the "cut-off" MOSFETs decreases and becomes V DD-(vn+vp). Decreasing V ds will decrease the effect of drain-induced barrier lowering (DIBL) so that the leakage currents decrease even more. In addition, the SVL circuit not only reduces the V gd of the "cut-off" MOSFETs but also reduces the V gc of the "turn-on" MOSFETs. Decreasing V gd reduces the GIDL currents of the "cut-off" MOSFETs and decreasing V gc decreases the

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gate-quantum-tunneling leakage currents of the load circuit will greatly decrease.

SRAM design & performance
We fabricated SRAMs with a 1K-bit (8b*8W*16W) memory-cell array incorporating an SVL circuit with an m of 1 or 2 using 45-nm technology. A photograph of the SRAM LSI chip is shown in Fig. 3. The channel widths of the pMOSFETs and nMOSFETs in the memory cells are 2.5 µm. Fig. 4 shows the simulated voltage levels at various nodes in the SRAM with the 1K-bit shown in Fig.  4a, the SVL circuit supplies a lower V D (1.03V) and a relatively higher V s (0.35V) to the memory cell array, and retains the memory cell data during stand-by. When CL goes to a high level, V D increases to V DD (1.8V), while V s decreases to V ss (0V),so the SRAM becomes active within about 600 psec. Fig. 4b shows the row address   (ADR) and word-line voltage(V w ) waveforms and fig. 4c shows the output datum (d 0 = '1') waveform. The "read" access time of the new SRAM is 536.9 psec, namely, almost the same as that (535.5 psec) of the conventional 1K-bit SRAM. Fig. 5 depicts the measured stand-by power (P STm1 ) of a 1K-bit memory-cell array based on an SVL circuit with an m of 1, that (P STm2 ) of a 1K-bit memory-cell array incorporating an SVL circuit with an m of 2,and that (P STcon ) of the conventional memory cell array. Fig. 5 also plots the stand-by power ratio.P STm2 is drastically reduced to 3.7nW, which is namely 5.4% of the P STcon (=69.1nW) at Vdd = 1.8V. Fig. 6 shows the measured waveforms at various nodes of an SRAM with a 1K-bit memory-cell array incorporating an SVL circuit with an m of 2. Fig. 6a, b, c and d are the 100-Mhz clock (clk), Read/Write control signal (WE),"Write data"(D i s) and "read data"(D o s), Respectively.
The active power (P AT ) of an SRAM with a 1K-bit memory-cell array based on the SVL circuit with an m of 2 at a clock frequency (f c ) of 200 MHz and a V DD of 1.8 V was 3.295 mW, which was almost as that (3.296nW) of a conventional 1K-bit SRAM. Table 1 summarizes the characteristics of 1K-bit, 45-nm CMOS SRAM.

Conclusion
We fabricated 1K-b SRAMs with a leakage current reduction circuit using a 45-nm CMOS process. The measured stand-by leakage power of the 1K-b SRAM memory cell array significantly decreased to 5.4% that of the conventional SRAM memory cell array, while the speed degradation and area overhead were negligible and the "write" operating margin was increased. We concluded that the developed SRAM incorporating the SVL circuit, which can retain data even in stand-by, will play a major role in future deep sub-100-nm CMOS SRAMs.