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A Low-leakage Current Power 45-nm CMOS SRAM

Affiliations

  • Dept. of Electronics and Communication Engineering, Thapar University, Patiala, India
  • Dept. of Electronics and Communication Engineering, Institute of Technology and Management, Gwalior

Abstract


A low leakage power, 45-nm 1Kb SRAM was fabricated. The stand-by leakage power of a 1K-bit memory cell array incorporating a newly-developed leakage current reduction circuit called a self-controllable voltage level (SVL) circuit was only 3.7 nW, which is 5.4% that of an equivalent conventional memory-cell array at a VDD of 1.8V. On the other hand, the speed remained almost constant with a minimal overhead in terms of the memory cell array area.

Keywords

SRAM, Memory Cell Array, Leakage Current

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References


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  • Mutoh S et al. (2008) A 1V multi-threshold voltage CMOS DSP with an efficient power management technique for mobile phone application. Digest of technical papers, IEEE Int. solid-state circuits conf. (ISSCC’96), FA 10.4, pp168-169.

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