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A Low-Power Hybrid Multiplication Technique for Higher Radix Hard Multiples Suppression

Affiliations

  • Department of Electronics and Communication Engineering, Heera College of Engineering and Technology, Kalliyode, Thiruvananthapuram - 695568, Kerala, India
  • Department of Electronics and Communication Engineering, K. S. Rangasamy College of Technology, Namakkal District - 637215, Tamil Nadu, India

Abstract


This paper presents a low-power higher radix multiplication algorithm based on Radix-16 32×32 bit Modified Booth Encoder (MBE). Hard multiples are the major factors for power consumption in higher radix MBE. This paper introduces the design of a Hybrid Multiplication Technique (HMT) to suppress the hard multiples that exist in a Radix-16 32×32 bit MBE. The proposed HMT uses Radix-8 and Radix-4 encoding technique along with Radix-16 to avoid the hard multiples. Experimental results based on Synopsys SDK 90nm, 1.32V standard-cell library show that the proposed HMT reduces power consumption up to 25% and 21% in comparison with conventional Radix-16 and Radix-8 MBE respectively. HMT equipped Radix-16 MBE also gives better performance than existing techniques with respect to frequency and power.

Keywords

Hard Multiples, Higher-Radix Modified Booth Multiplier, Low-Power, Slack, Synthesis

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References


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