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28nm FPGA based Power Optimized UART Design using HSTL I/O Standards
UART abbreviated as Universal Asynchronous Receiver Transmitter is one of the essential element of communication system. It is being mostly used when there is a short-distance, between computer and peripherals. Whenever there is low-cost data exchange or the speed required for transmission is not high, UART’s are also being used there. For the achievement of compact, stable and reliable data transmission, the implementation of UART with VHDL language can be integrated into FPGA. The Total power and Junction temperature of UART have been analyzed in the following paper when it is operating on different I/O standards of HSTL (HIGH SPEED TRANSCEIVER LOGIC) logic family and different range of frequencies from 1 GHz to 46 GHz. Analysis have also been done for two different 28nm FPGA’s which helps to compare the total power reduction at two different FPGA technology so that the best suited FPGA for UART design consuming the least could be discovered. After analysis, it has been concluded that 91.96% of the total power can be saved in the case Kintex-7 and 91.98% of total power can be preserved in case of Artix-7 by operating the design at a frequency of 1 GHz. On the other hand the Junction temperature has been reduced to 11.84% in case of Kintex-7 and it has been reduced to 15.28% in case of Artix-7.
Artix, FPGA, HSTL, Kintex, UART
- Norhuzaimin J, Maimun HHH. The design of high speed UART. IEEE Asia-Pacific Conference on Applied Electromagnetics (high speed UART design), APACE 2005; 2005 Dec; p. 5.
- Hu LK, Wang QCH. UART-based reliable communication and performance analysis. Computer Engineering. 2006 May; 32(10):15–21.
- Idris MY, Yaacob M. A VHDL implementation of BIST technique in UART design. 2003 Oct 15-17; 4:1450–4.
- Xu LY. Realization of UART Communication Based on FPGA. Microcomputer Information. 2007; 23(35):218–9.
- Kalia K, Pandey B, Nanda K, Malhotra S, Kaur A, Hussain DMA. Pseudo open drain IO standards based energy efficient solar charge sensor design on 20nm FPGA. 11th IEEE International Conference on Power Electronics and Drive Systems (PEDS 2015); 2015 Jun; Sydney, Australia. p. 9–12.
- Singh S, Kaur A, Pandey B. Energy efficient flip flop design using voltage scaling on FPGA. IEEE Sixth India International Conference on Power Electronics (IICPE); 2014 Dec 8–10; NIT Kurukshetra. p. 1–5.
- Kaur A, Singh S, Pandey B, Kaur R. Clock gating based low power efficient universal gurmukhi unicoder design on FPGA. International Symposium, ICTT 2014; 2014 Nov; Chitkara University.
- Kaur A, Singh G, Pandey B, Fazili B. Capacitance scaling based green gurumukhi Unicode reader design for natural language processing. 9th Editon IEEE International Conference on Computing for Sustainable Global Development (INDIACOM). 2015 March 11-13; Bharati Vidyapeeth, Delhi.
- Pandey B, Singh G. Simulation of HSTL IO standard based energy efficient Punjabi Unicode reader on FPGA. IEEE International Conference on Computational Intelligence and Communication Networks (CICN) 2014. p. 62–4.
- Singh S, Jain A, Kaur A, Pandey B. Thermal aware low power universal asynchronous receiver transmitter design on FPGA. IEEE 6th International Conference on Computational Intelligence and Communication Networks (CICN); 2014 Nov. 14–16; Udaipur. p. 939–42.
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