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3D VLSI Non-Slicing Floor Planning using Modified Corner List Representation

Affiliations

  • Department of Electronics and Communication Engineering, Kongu Engineering College, Perundurai – 638052, Tamil Nadu, India
  • Department of Electrical and Electronics Engineering, Dr. Mahalingam College of Engineering and Technology, Pollachi - 642003, Tamil Nadu, India

Abstract


Background: Floor planning is important step in physical design automation of VLSI circuits, because it gives an early feedback on the architectural design. It is the process of finding the position of the module such that no two modules overlap with each other. Methods: In order to have an efficient floor plan, the total area occupied by the modules should be minimum. So, non-slicing floor plan is used to find an optimal floor plan layout. To represent non-slicing floor plan, a number of representations are proposed. Findings: To encompass billions of transistors in an Integrated Circuit (IC), 3Dimensional (3D) IC is preferred instead of 2D. In this paper, a novel 3Dimensional (3D) non-slicing floor planning representation called Modified Corner List (MCL) algorithm is proposed and properties of MCL algorithm is derived. The proposed algorithm is illustrated using Microelectronics Centre of North Carolina (MCNC) benchmark circuits and simulation results shows that it is very effective for 3D floor plan representation. Improvements: The proposed algorithm works well for small number of modules. As the number of module increases, computational time taken by the algorithm also increases. The above problem can be solved by applying heuristic algorithm in association with MCL strategy to find near optimal placement in reduced run time.

Keywords

MCNC Benchmark Circuits, Modified Corner List, 3D Non-Slicing Floor Plan, VLSI

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