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3D VLSI Non-Slicing Floor Planning using Modified Corner List Representation


  • Department of Electronics and Communication Engineering, Kongu Engineering College, Perundurai – 638052, Tamil Nadu, India
  • Department of Electrical and Electronics Engineering, Dr. Mahalingam College of Engineering and Technology, Pollachi - 642003, Tamil Nadu, India


Background: Floor planning is important step in physical design automation of VLSI circuits, because it gives an early feedback on the architectural design. It is the process of finding the position of the module such that no two modules overlap with each other. Methods: In order to have an efficient floor plan, the total area occupied by the modules should be minimum. So, non-slicing floor plan is used to find an optimal floor plan layout. To represent non-slicing floor plan, a number of representations are proposed. Findings: To encompass billions of transistors in an Integrated Circuit (IC), 3Dimensional (3D) IC is preferred instead of 2D. In this paper, a novel 3Dimensional (3D) non-slicing floor planning representation called Modified Corner List (MCL) algorithm is proposed and properties of MCL algorithm is derived. The proposed algorithm is illustrated using Microelectronics Centre of North Carolina (MCNC) benchmark circuits and simulation results shows that it is very effective for 3D floor plan representation. Improvements: The proposed algorithm works well for small number of modules. As the number of module increases, computational time taken by the algorithm also increases. The above problem can be solved by applying heuristic algorithm in association with MCL strategy to find near optimal placement in reduced run time.


MCNC Benchmark Circuits, Modified Corner List, 3D Non-Slicing Floor Plan, VLSI

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  • Sivaranjani P, Kumar AS. Thermal-aware non-slicing VLSI floor planning using a smart decision-making PSO-GA based hybrid algorithm, circuits, systems and signal processing. 2015 Nov; 34(11):3521–42.
  • Gomes SV, Sasipriya P, Bhaaskaran VSK. A low power multiplier using a 24-transistor latch adder. Indian Journal of Science and Technology. 2015 Aug; 8(19):1–5.
  • Bernstein K, Andry P, Cann J, Emma P, Greenberg D, Haensch W, Young A. Interconnects in the third dimension: Design challenges for 3D ICs. Proceedings of the 44th annual Design Automation Conference: San Diego CA; 2007 Jun 4-8. p. 562-–7.
  • Cheng L, Deng L, Wong MD. Floor planning for 3D VLSI design. Proceedings of the 2005 Asia and South Pacific Design Automation Conference; ACM; 2005 Jan 18-21. p. 405–11.
  • Wang R, Cheng CK. On the complexity of graph cuboidal dual problems for 3D floor planning of integrated circuit design. Proceedings of the 19th ACM Great Lakes symposium on VLSI; 2009. p. 257–62.
  • Otten, RHJM. Automatic floor plan design. Proceedings of the 19th Design Automation Conference: Las Vegas NV; 1982 Jun 14-16. p. 261–7.
  • Yamazaki H, Sakanushi K, Nakatake S, Kajitani Y. The 3D-packing by meta data structure and packing heuristics. IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. 2000 Apr; 83(4):639–45.
  • Kohira Y, Kodama C, Fujiyoshi K, Takahashi A. Evaluation of 3D-packing representations for scheduling of dynamically reconfigurable systems. Proceedings 2006 IEEE International Symposium on Circuits and Systems: Island of Kos; 2006 May 21-24. p. 21–34.
  • Murata H, Fujiyoshi K, Nakatake S, Kajitani Y. VLSI module placement based on rectangle-packing by the sequence-pair. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.1996 Dec; 15(12):1518–24.
  • Yuh PH, Yang CL, Chang YW, Chen HL. Temporal floor planning using 3D-subTCG. Proceedings of the 2004 Asia and South Pacific Design Automation Conference IEEE Press: Yohohama, Japan; 2004 Jan 27-30. p. 725–30.
  • Lin JM, Chang YW. TCG: A transitive closure graph-based representation for non-slicing floor plans. Proceedings of the 38th annual Design Automation Conference: 2001. p. 764–9.
  • Yamagishi H, Ninomiya H, Asai H. Three dimensional module packing using 3DBSG structure. IEEE Congress on Evolutionary Computation. 2005; 5:1069–74.
  • Nakatake S, Fujiyoshi K, Murata H, Kajitani Y. Module acking based on the BSG-structure and IC layout applications. IEEE Transactions on Computer Aided Design. 1998 Jun; 17(6):519–30.
  • Cong J, Wei J, Zhang Y. A thermal-driven floor planning algorithm for 3D ICs. In IEEE/ACM International Conference on Computer-Aided Design; 2004 Nov 7-11. p. 306–13.
  • Okal B. 3D CBL: An efficient algorithm for general 3-dimensional packing problems. Automation Seminar; 2012. p. 1–24.
  • Hong X, Huang G, Cai Y, Gu J, Dong S, Cheng CK, Gu J. Corner block list: An effective and efficient topological representation of non-slicing floor plan. Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design: San Jose CA; 2000 Nov 5-9. p. 8–12.
  • Hoo CS, Jeevan K, Ganapathy V, Ramiah H. Variable-order ant system for VLSI multi objective floor planning. European Journal of Applied Soft Computing. 2013 Jul; 13(7):3285–97.
  • Alupoaei S, Katoori S. Ant Colony System application to macrocell overlap removal. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2004 Oct; 12(10):1118–23.


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