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16-Bit Fast Addition Computation using Domino Logic
Objectives: A 16-bit carry look ahead adder is implemented in domino CMOS logic is presented in this paper. The proposed work comprises of two separate 8-bit carry chains. Statistical Analysis: This is evaluated using TANNER EDA tool. The schematics are drawn in s-edit, netlists are generated using T-spice and the waveforms are verified using waveform viewer or w-edit. Layouts can also be created using SDL (Schematic Drawn Layout), by importing netlist in L-edit. Findings: Due to the split carry chains in the adder, the speed of computation is increased, at the cost of area, when compared with ordinary carry look ahead adder. As we know that the use of domino logic reduces the power consumption, but as switching occurs many times power consumption is increased, that is the switching power of the system is increased. Applications: In VLSI system reducing the multipliers and increasing the adders is the main factor, thus in place of those adders if this split carry adders are used, the speed will be increased further.
Domino Logic, Fast Addition, 16-bit Carry Look Ahead Adder, Split Carry, Tanner EDA.
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