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Analysis of High Performance Parallel Computing Instruction Sets
This study explores existing design principles of the processor architecture and identifies future design approach that will help to solve existing business problems that are operable on the scalable environment. We considered the two broader classifications of the instruction sets- RISC and CISC and analyzed the ways to improve the performance of the existing processor design approach. Findings show that all the design principles have been made for different engineering level points to work on the different kinds of task that are specific to the respective fields and SIMD data can be handled well in vector processing environments. Improvements can be made while choosing the design environment based on the business problem and significant design improvement can make to overcome the existing performance-related issues.
CISC, MIMD, MISD, RISC, SIMD, SISD, Vector Processing, VLIW.
- Bhandarkar D, Clark DW. Performance from architecture: Comparing an RISC and a CISC with similar hardware organization.In Proceedings of the 4th International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS IV; New York, NY, USA: ACM. 1991. p. 310–9. DOI: 10.1145/106972.107003.
- George AD. An overview of RISC vs CISC. Proceedings of the 22nd Southeastern Symposium on System Theory; 1990. p. 436–8. DOI: 10.1109/SSST.1990.138185.
- Dornika DM, Ravi KS, Krishna PG. An efficient identification of dynamic faults using CAN and ARM7 in a wind turbine. Indian Journal of Science and Technology. 2016; 9(17). DOI: 10.17485/ijst/2016/v9i17/93112.
- Jeff AS, Owens JD. Multi-GPU MapReduce on GPU clusters.Proceedings of the 2011 IEEE International Parallel and Distributed Processing Symposium; Washington, DC, USA: IEEE Computer Society. 2011. p. 1068–79. DOI: 10.1109/IPDPS.2011.102.
- Wang Y, Li B, Luo R, Chen Y, Xu N, Yang H. Energy efficient neural networks for big data analytics. 2014 Design, Automation Test in Europe Conference Exhibition (DATE); 2014. p. 1–2. DOI: 10.7873/DATE.2014.358.
- RISC versus CISC architecture. Available from: http:// www2.cs.siu.edu/~cs401/Textbook/ch4.pdf
- Isen C, John LK, John E. A tale of two processors: Revisiting the RISC-CISC debate. Proceedings of the 2009 SPEC Benchmark Workshop on Computer Performance Evaluation and Benchmarking; Berlin, Heidelberg: Springer-Verlag. 2009. p. 57–76. DOI: 10.1007/978-3-540-93799-9_4.
- Blem E, Menon J, Sankaralingam K. Power struggles: Revisiting the RISC vs. CISC debate on contemporary ARM and x86 architectures. 2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA); 2013. p. 57–76. DOI: 10.1109/HPCA.2013.6522302.
- Garth SCJ. Combining RISC and CISC in PC systems. In IEE Colloquium on RISC Architectures and Applications, 10/1-10/5; 1991.
- Khazam J, Mowery D. The commercialization of RISC: Strategies for the creation of dominant designs. Research Policy. 1994 Jan; 23(1):89–102. DOI: 10.1016/00487333(94)90028-0.
- Vijaykumar S, Saravanakumar SG, Balamurugan M. Unique sense: Smart computing prototype for industry 4.0 revolution with IOT and bigdata implementation model. Indian Journal of Science and Technology. 2015 Dec; 8(35). DOI: 10.17485/ijst/2015/v8i35/86698.
- Dinesh D, Kumar RM. Physical design implementation of 16 bit RISC processor. Indian Journal of Science and Technology. 2016 Sep; 9(36). DOI: 10.17485/ijst/2016/ v9i36/102911.
- Kumar JV, Raju BN, Babu MV, Sreelekha K, Ramanjappa T. Implementation of low power pipelined 64-bit RISC processor with unbiased FPU on CPLD. Indian Journal of Science and Technology. 2016 Sep; 9(33). DOI: 10.17485/ ijst/2016/v9i33/89815.
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