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Analysis of High Performance Parallel Computing Instruction Sets

Affiliations

  • School of Computer Science, Engineering and Applications, Bharathidasan University, Trichy - 620024, Tamil Nadu, India
  • School of Computer Science, Engineering and Applications, Bharathidasan University, Trichy - 620024, Tamil Nadu, India
  • 6th SENSE, An Advanced Research and Scientific Experiment Foundation, kumbakonam - 612001 Tamil Nadu, India

Abstract


This study explores existing design principles of the processor architecture and identifies future design approach that will help to solve existing business problems that are operable on the scalable environment. We considered the two broader classifications of the instruction sets- RISC and CISC and analyzed the ways to improve the performance of the existing processor design approach. Findings show that all the design principles have been made for different engineering level points to work on the different kinds of task that are specific to the respective fields and SIMD data can be handled well in vector processing environments. Improvements can be made while choosing the design environment based on the business problem and significant design improvement can make to overcome the existing performance-related issues.

Keywords

CISC, MIMD, MISD, RISC, SIMD, SISD, Vector Processing, VLIW.

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References


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