Indian Journal of Science and Technology

Abstract

SRAMs are important building blocks in many digital applications, such as microprocessors and cache memories. Decoders are the significant components in SRAMs. Address decoder is vital part of SRAM memory. Choice of capacity cell and read operation is relies on upon decoder. Henceforth, execution of SRAM is relies on upon these parts. This work studies the location decoder for SRAM memory, focusing on deferral streamlining and control effective circuit systems. We have focused on ideal decoder structure with slightest number of transistors to diminish range of SRAM. Usually, in Memory Chip, it consumes almost fifty percent of the total chip access time and power. Parameters which has to be considered while designing an address decoders are, first appropriate circuit technique has to be chosen and the second thing is sizing constrains of the transistors. Modified hybrid type of decoding topology is illustrated and it is compared with traditional type decoders which include both static and dynamic types using 180 nm CMOS technology in Cadence Virtuoso environment.
Keywords: Buffer Control, Cadence and Power Consumption, SRAM, Static Decoder