Indian Journal of Science and Technology

Abstract

Background: In all electronic based applications, memory design is crucial which decides the performance of the system. In present technology nodes reliability is a growing concern where the static SRAM memories are not able to store the contents for a longer period of time. Reliability is mainly due to aging degradation which characterises BTI (Bias Temperature Instability) and HCI (Hot Carrier Injection) resulting in permanent damage to MOS parameters and as a result MOS deviates slightly from its normal behaviour. Method: In order to maintain the performance of SRAM within considerable PVT (Process Voltage Temperature) boundaries over a period of time, all the six MOSFETs strength should be dynamically adjusted. So that the ground bounce can be minimised at critical nodes of the bit-cell and stability can be maintained. Findings: In this paper, statistical analysis is performed on 14nm designed 6T-SRAMs and various Shmoo -plots have been developed for different PVTs considering aging impact for a span of 10 years. Analysis was performed for both SRAM read and write operation. All simulations were carried out using HSPICE-2013 version and aging models of MOSRA level-3 version 103.1. Conclusion: From the analysis it clearly evident that read is slightly degraded by 15%-25% were the operating voltage ranges has been degraded. In this design core voltage has been increased from 0.96v to 1.08v and periphery voltage from 0.5v to 0.62v. Thus to ensure the same performance after 10 years the operational voltage has to be increased by 20%.
Keywords: Aging and FINFET, 6T-SRAM