Indian Journal of Science and Technology
Year: 2015, Volume: 8, Issue: 33, Pages: 1-5
Vellore Institute of Technology, Vellore - 632014, Tamil Nadu, India; [email protected]
Background: Tag caches models are proposed in improving cache performance. The tag cache and processor cache are in high energy mode in the proposed models. To reduce the power consumption in tag cache model is aim of this paper. Methods: A cache model to save power in tag cache model of exclusive cache is proposed. The SPEC2K benchmarks run against Simplescalar Toolkit is used for simulations. Routines in C language are written to simulate the proposed model and traditional processor cache models. The SPEC2K addresses are run with C program. The power consumption is calculated from Quartus2 using Verilog code for both proposed and traditional models. The proposed model is synthesized in Quartus2. The average memory access time between proposed and traditional models is compared. The power consumption is compared between traditional and proposed models. Findings: The power consumption in tag cache is improved in the proposed model by introducing AND gate. The average memory access time is constant with the base model. A power saving of 49% was observed in the proposed model over the model proposed in5 with no change in average memory access time. The author in5 reported energy saving of 23% with comparable average memory access time over model presented in3 . The proposed model is scalable to higher cache levels. The proposed model can be implemented in any processor (uni-processor or multiprocessor)having exclusive cache model. Applications/ Improvements: The proposed model can be extended for multilateral caches with suitable logic.
Keywords: Cache Architecture, Cache Power Saving, Exclusive Cache, Logic Circuit, Tag Cache Model
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