Cuckoo Search Optimization Algorithm based Hardware Task Placement and Routing in CAD of FPGAs Design Flow

B  Premalatha  and S  Umamaheswari

doi:10.17485/ijst/2016/v9i6/69913

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Cuckoo Search Optimization Algorithm based Hardware Task Placement and Routing in CAD of FPGAs Design Flow

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Indian Journal of Science and Technology

DOI: 10.17485/ijst/2016/v9i6/69913

Year: 2016, Volume: 9, Issue: 6, Pages: 1-8

Original Article

Cuckoo Search Optimization Algorithm based Hardware Task Placement and Routing in CAD of FPGAs Design Flow

B. Premalatha^* and S. Umamaheswari

Department of Electronics and Communication Engineering, Coimbatore Institute of Technology, Coimbatore – 641014, Tamil Nadu, India; [email protected], [email protected]

*Author for Correspondence
B. Premalatha
Department of Electronics and Communication Engineering, Coimbatore Institute of Technology, Coimbatore – 641014, Tamil Nadu, India; [email protected]

This work is licensed under a Creative Commons Attribution 4.0 International License.

Abstract

In this paper, Cuckoo search optimization algorithm based placement of tasks in FPGAs is introduced and was compared with PSO, ARPSO and GSA. Both single and multiobjective constraints based fitness function is formulated. The simulation result shows that CSO outperforms the others. By tuning the design parameters of CSO algorithm, the FPGA Placement process performs better

Keywords: FPGA Placement, Optimization, Single and Multiobjective Constraints, Wirelength and Area Minimization