• P-ISSN 0974-6846 E-ISSN 0974-5645

Indian Journal of Science and Technology


Indian Journal of Science and Technology

Year: 2017, Volume: 10, Issue: 3, Pages: 1-8

Original Article

Design and Implementation of FPGA based 64-bit MAC Unit using VEDIC Multiplier and Reversible Logic Gates


Now a days in VLSI technology size, power, and speed are the main constraints to design any circuits. In normal multipliers delay will be more and the number of computations also will be more. Because of that speed of the circuits designed with the normal multipliers will be low and it will consume more power. This paper describes Multiply and Accumulate Unit using Vedic Multiplier and DKG reversible logic gates. The Vedic multiplier is designed by using UrdhavaTriyagbhayam sutra and the adder design is done by using reversible logic to perform high speed operations. Reversible logic gates are also the essentialconstraint for the promising field of Quantum computing. The UrdhavaTriyagbhayam multiplier is used for the multiplication function to reduce partial products in the multiplication process and to get high concert and less area.The reversible logic is used to get less power. The MAC is designed using Verilog code, simulation, synthesis is done in both RTL compiler using Xilinx and implemented on Spartan 3e FPGA Board.

Keywords: MAC, Reversible Gates, Vedic Multiplier


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