Indian Journal of Science and Technology
Year: 2019, Volume: 12, Issue: 29, Pages: 1-6
V. Brunda*, D.K. Nayana and K. Hashwitha
School of ECE, REVA University, Banglore, India; brun[email protected], [email protected], [email protected]
*Author for correspondence
School of ECE, REVA University, Banglore, India; [email protected]
Objectives: For Orthogonal Frequency Division Multiplexing (OFDM), Fast Fourier Transform (FFT) processoris required. So, in this work, a variable point Pipelined FFT processor is designed by utilizing Verilog language. Further transmitter and receiver blocks are designed to form OFDM system. Methods: Speed enhancement is the key area which is been looked into this project work. Pipelined Architecture that is going to be implemented is RS2DF (Radix-2 Single path Delay Feedback). Standard FPGA Flow is adapted to implement this project i.e., right from specification to bit file generation. Simulations and Synthesis will be done using Questasim and Xilinx ISE. Verilog Simulations will be compared with in-built MATLAB FFT Core. MATLAB is used for reference and verification. Findings: This Project clarified the usage of FFT IP and OFDM in Xilinx ISE focusing on a specific family of FPGA. The execution of the proposed algorithm ought to perform superior to anything the base algorithm with the all-out basic way getting additionally advanced along these lines expanding the speed of activity. maximum operation frequency achieved was 236.189MHz but in base paper maximum operation frequency was 30Mhz. The systems utilized are Interna1 and externa1 Pipe1ining of modules and Distributed LUT based idea, the target of the above methods is to lessen the basic way deferral and increment the general speed of activity of structure, the disadvantage is the increments in area and output latency. Area is not of a much issue as present day days FPGAs has immense measure of assets. Output 1atency should be taken consideration with additional rationale at whatever point FFT is coordinated with other system modules. Application: The project depicts technique for streamlining timing basic ways of FFT to work at higher-speeds, to be utilized as a feature of LTE Protoca1 or any wire1ess protoco1 such as WLAN and LDACS.
Keywords: Fast Fourier Transform (FFT), Hardware Description Language (HDL), Orthogonal Frequency Division Multiplexing (OFDM), Pipeline, Verilog
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