• P-ISSN 0974-6846 E-ISSN 0974-5645

Indian Journal of Science and Technology


Indian Journal of Science and Technology

Year: 2019, Volume: 12, Issue: 36, Pages: 1-5

Original Article

Design and Implementation of High Speed Viterbi Decoder and Convolution Encoder for SDR


Objectives: Data transmission in wireless communication system will be affected by noise. The Viterbi decoder and convolutional encoder are best suited for forward error detection and correcting codes for a channel. Methods: The study proposes convolutional encoder with 1/2 code rate and constrained length of 3. An improved architecture which optimizes critical path delay is proposed to achieve higher speeds. The design is carried out in MATLAB. The simulation of proposed architecture is done using XILINX 14.1 and implementation is done using FPGA SPARATAN 3AN. Findings: Software defined radio uses different modulation and encoding procedures and techniques by varying its configuration. In recent years, it has earned a great reputation for its flexible ability to adapt different procedures and techniques without changing the existing hardware. SDR offers a flexible method of communication and decreasing the cost complexity problem. The Viterbi decoder exploits advantages in SDR applications mainly because of area efficiency and speed. Application: The Viterbi decoder will be able to correct and detect one-bit error at the input bit stream of data. For high speed SDR applications the proposed architecture is suitable.

Keywords: Convolutional Encoder, Viterbi, FPGA, SDR


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