Indian Journal of Science and Technology
Year: 2016, Volume: 9, Issue: 7, Pages: 1-6
C. Uthaya Kumar1 and B. Justus Rabi2
The aim of the current research work is to improve the architectural performances of digital filter. An efficient Multiplication and Accumulation (MAC) unit called “Russian Peasant Multiplier” is modified in this research work to alleviate the filter architecture. In proposed methods, switching activities of multiplier values has been validated by using only left shifters only, where as traditional Russian peasant multiplication has two shifters namely left and right respectively for validating multiplier values. Reduced Wallace Tree Generation (RWTG) method has been used to re-arrange the partial product results. Further Modified Square Root Carry Select Adder (MSQRTCSLA) has been incorporated into RWTG for performing accumulation operation of Multiplication. Proposed digital FIR Filter offers 45.61% improvements in hardware slices, 42.02% improvements in Slice Flip-flops, 22.36% improvements in sequential delay, 1.56% improvements in minimum input arrival time before clock, 0.86% improvements in maximum output required time after clock, 19.52% improvements in dynamic power and 18.32% improvements in total power consumption than traditional Russian peasant multiplication based digital FIR filter. In future, proposed MAC based FIR filter architecture will be absolutely suited to Software Defined Radio (SDR) and Orthogonal Frequency Division Multiplexing (OFDM) based data communication applications for improving hardware speed and power consumptions.
Keywords: Reduced Full Adder, Reduced Gate Level Logic, Reduced Half Adder, VLSI based filter design, Wallace Tree Generation
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