Indian Journal of Science and Technology
Year: 2015, Volume: 8, Issue: Supplementary 2, Pages: 1-5
Md. Shabaz* , Anand Patel, Suraj Iyer, S. Ravi and Harish M. Kittur
VLSI Division, SENSE, VIT University, Vellore, Tamil Nadu, India; [email protected]
Due to the continual downscaling of technology, System on Chip (SoC) is becoming denser and denser with multiple IP cores within. As the number of cores within a SoC increase, so does the number of faults within the chip. Along with the designing aspect of a chip, design for testability too is a major area of concern. Testing methods like Built-In-Self-Test (BIST) allow the chip to test itself without the need for external testing equipment. Test patterns for BIST are generated using Linear Feedback Shift Register (LFSR) which produces test vectors in a pseudo random manner. This paper concentrates on improving the hardware in terms of area and number of logical gates in the 2-D LFSR used for testing an SoC with multiple IP cores so that vectors in various patterns can be generated using a single reconfigurable 2 Dimensional LFSR. The proposed technique is much more useful for testing System on a Chip with large number of cores as the same configuration network is used to test different SoC cores.
Keywords: Built-In-Self-Test (BIST), Linear Feedback Shift Register (LFSR), Reconfigurable 2-D LFSR, System-on-Chip (SoC)
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