• P-ISSN 0974-6846 E-ISSN 0974-5645

Indian Journal of Science and Technology


Indian Journal of Science and Technology

Year: 2016, Volume: 9, Issue: 29, Pages: 1-9

Original Article

Efficient Hardware Architecture of EEG Analyzer for Determining the Depressive Disorders


Background/Objectives: In this paper, economical hardware design of the Electroencephalography (EEG) is planned for deciding the depressive disorders. The goal of this paper is development of moveable device supported encephalogram analysis targeted at analysis of mental disorders. Methods/Statistical Analysis: We presented a modified architecture of the Power Spectral Density (PSD) and also Spectral Asymmetry Index (SASI) for depression detection. Finding: The proposed architecture of the PSD computation reduces the computational complexity and hardware requirement due to the adaption of the merging process. SASI algorithm reveals the disturbed state of the brain. Improvements/Application: The planned hardware design is meant victimization Field Programmable Gate Array (FPGA). This design is simulated and tested victimization VHDL and synthesized victimization Xilinx ISE fourteen.
Keywords: Electroencephalography (EEG), Field Programmable Gate Array (FPGA), Merging Process, Power Spectral Density (PSD), Spectral Asymmetry Index (SASI)


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