• P-ISSN 0974-6846 E-ISSN 0974-5645

Indian Journal of Science and Technology


Indian Journal of Science and Technology

Year: 2017, Volume: 10, Issue: 14, Pages: 1-5

Original Article

Efficient Modified Booth Multiplier for Signal Processing Applications


The two’s complement approach plays a vital role in reducing Partial product Rows count in signed bit multiplier. In this paper proposed a multiplier which reduces the partial product rows by Modified Booth techniques with less delay. This high performance 2’s complement multiplier is used in embedded cores. This work was implemented in the Xilinx software and simulation results were obtained for the different applications. Applications such as FIR filter and Image processing requires high accuracy and smaller size multipliers. The image and filter interfacing is done with the help of MATLAB software. 

Keywords: Image Processing, MATLAB, Modified Booth Technique, Partial Product, Xilinx


Subscribe now for latest articles and news.