Indian Journal of Science and Technology
Year: 2017, Volume: 10, Issue: 4, Pages: 1-3
Abhay Saxena1*, Chandrashekhar Patel1 and M. Sadiq Ali Khan2
*Author for the correspondence:
Dev Sanskriti Vishvavidyalaya, Haridwar - 249411, Uttarakhand, India; [email protected]
In our work we have designed CRC using the LVCMOS IO standards which are stands for Low Voltage Complementary Metal Oxide Semiconductor. In this work we have worked with four kinds of LVCMOS (LVCMOS 12, LVCMOS 15, LVCMOS 18, LVCMOS 25). For LVCMOS 12 when we scaled down the frequency form 50GHz to 10 GHz we found 64.41% reduction in total power. For LVCMOS 15 when we change down the frequency form 50GHz to 10GHz we found 67.58% reduction in total power. For LVCMOS 18 when we scaled down the frequency form 50GHz to 10 GHz we found 69.54% reduction in total power. In last when we reduced the frequency form 50GHz to 10GHz in LVCMOS 25 we found 64.41% reduction in total power. Our CRC design is implemented on Virtex-6 FPGA family.
Keywords: 40 nm FPGA, CRC, Energy Efficient, Low Power, LVCMOS IO Standard
Subscribe now for latest articles and news.