FPGA and ASIC Implementation of Systolic Arrays for the Design of Optimized Median Filter in Digital Image Processing Applications

Kalyan Sagar Kadali   and L  Rajaji

doi:10.17485/ijst/2014/v7sp7.20

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FPGA and ASIC Implementation of Systolic Arrays for the Design of Optimized Median Filter in Digital Image Processing Applications

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Indian Journal of Science and Technology

DOI: 10.17485/ijst/2014/v7sp7.20

Year: 2020, Volume: 7, Issue: Supplementary 7, Pages: 99–103

Original Article

FPGA and ASIC Implementation of Systolic Arrays for the Design of Optimized Median Filter in Digital Image Processing Applications

Kalyan Sagar Kadali^1* and L. Rajaji²

1 Department of Electrical and Electronics Engineering, AMET University, Chennai, India; kalyansagar.k@gmail.com
2 Department of Electrical and Electronics Engineering, ARM College of Engineering and Technology, Chennai, India

This work is licensed under a Creative Commons Attribution 4.0 International License.

Abstract

Background/Objectives: A new systolic algorithm for median filtering is analyzed in this paper, this algorithm is suitable for VLSI implementation to design optimized median filter. Methods/Statistical analysis: The modified sort algorithm avoiding the main problem of the median filter is its high computational cost (for sorting N pixels, the temporal complexity is O (N·log N), even with the most efficient sorting algorithms, the clock cycle time is equal to the propagation delay of a simple comparator circuit. Results/Findings: The hardware requirements of the architecture are significantly lower than those of previously reported systolic array architectures. An implementation of 8-bit word length 3X3 window size filter in an ALTERA EP1C3T100C6 FPGA achieved a clock rate in excess of 197 MHz with 85 cells only. Conclusion/Application: An improved algorithm has been proposed to address to problem of median filter that is high computation time is encountered.

Keywords: Median Filter, Processing Element, Systolic Algorithm