Indian Journal of Science and Technology
Year: 2010, Volume: 3, Issue: 4, Pages: 365-368
Sheetal U. Bhandari1 , Shaila Subbaraman2 , Shashank Pujari3 and Rashmi Mahajan4*
1, 3, 4 Dept. of Microelectronics and VLSI Design, International Institute of Information Technology, Pune-411057 India
2 Department of Electronics Engineering, Walchand College of Engg., Sangli 416415 India
[email protected] , [email protected] , [email protected] , [email protected]
Few FPGAs support creation of partially reconfigurable systems when compared to traditional systems based on total reconfiguration. This allows dynamic change of the functionalities hosted on the device when needed and while the rest of the system continues its working. Runtime partial reconfiguration of FPGA is an attractive feature which offers countless benefits across multiple industries. Xilinx has supported partial reconfiguration for many generations of devices. This can be taken advantage of substituting inactive parts of hardware systems and to adapt the complete chip a different requirement of an application. This paper describes an innovative implementation for real time audio and video processing using run time internal partial reconfiguration. System is implemented on Virtex-4 FPGA. Internal reconfiguration is handled using internal configuration access port (ICAP) driven by soft processor core. The considerable savings in device resources, bit stream size and configuration time is observed and tabulated in this paper.
Keywords: Reconfigurable computing; partial reconfiguration; run time reconfiguration; internal reconfiguration.
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