Indian Journal of Science and Technology
Year: 2018, Volume: 11, Issue: 19, Pages: 1-6
Geetanjali Udgirkar and G. Indumathi
*Author for correspondence
Cambridge Institute of Technology, Krishnarajapuram − 560036, Bangalore, Karnataka, India; [email protected]
Objectives: Timing driven VLSI routing is a challenging problem considering that the number of interconnects in todays’ technology design nodes is growing rapidly. VLSI or FPGA global routing is difficult problem considering the complexity and large size of present day IC designs. Methods/Statistical analysis: Net weighing algorithms for timing driven placement are effective way of optimizing delays during routing of designs. Timing driven routing with net weighting approach has not been explored in the past. Findings: We present two novel timing driven routing algorithm which is based on weighting of the critical nets. In the first method slack of the net is considered in evaluating the criticality of the net, whereas, in the second method we consider exponent of the criticality of the pin. These weights are then applied to all the nets while performing timing driven global routing. Improvements: The results of our experiments are encouraging, wherein, we obtain an improvement of 17.38% and 22.35% over VPR in the weighing schemes called Method A and Method B respectively
Keywords: Global Routing, Net Weighting Method, VLSI Routing
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