Optimization of Sram array Structure for Energy Efficiency Improvement in advanced CmOS Technology

J  S  ashwin; J  S  Praveen and N  Manoharan

doi:10.17485/ijst/2014/v7sp6.2

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Optimization of Sram array Structure for Energy Efficiency Improvement in advanced CmOS Technology

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Indian Journal of Science and Technology

DOI: 10.17485/ijst/2014/v7sp6.2

Year: 2020, Volume: 7, Issue: Supplementary 6, Pages: 35–39

Original Article

Optimization of Sram array Structure for Energy Efficiency Improvement in advanced CmOS Technology

J. S. ashwin^*, J. S. Praveen and N. Manoharan

AMET University, Chennai, India; jsashwin2010@gmail.com, Praveenjs1985@gmail.com, directorresearch@ametuniv.ac.in

This work is licensed under a Creative Commons Attribution 4.0 International License.

Abstract

This paper explores the design and analyze of SRAM array structure to decrease the power dissipation and to increase the energy efficiency. The SRAM array structure with high energy efficiency can be achieved with wider array structure with fewer rows than columns particularly in low supply voltage. The proposed analysis shows that the SRAM array structure optimization can improve the energy efficiency up to 20% at the same supply voltage.

Keywords: Optimization, SRAM Array, Energy Efficiency, CMOS Technology