• P-ISSN 0974-6846 E-ISSN 0974-5645

Indian Journal of Science and Technology


Indian Journal of Science and Technology

Year: 2016, Volume: 9, Issue: 29, Pages: 1-6

Original Article

Reliable High Performance Multiplier with Adaptive Hold Logic for Aging Awareness


Background: Digital multipliers, the most important part which is used to implement most of the digital processing and arithmetic applications such as Filters, FFT’s, etc. As the rapid developments in technology required, many researchers are going to design multipliers which offers an efficient design aspect with respect to the speed and power consumption. Statistical analysis: Multipliers are the key functional units in various applications. The transistor speed is reduced due to bias temperature instability effects. When this effect extends in distant future, the system may not work properly due to timing infraction. Findings: The overall performance of these systems depends on the multiplier’s throughput. The Negative Bias Temperature Instability (NBTI) effect occurs when a pMOS transistor is under negative bias (Vgs = −Vdd), which results the increase in the threshold voltage of the pMOS transistor, hence the delay in the multiplier is increased. In the same way, positive bias temperature instability, occurs when an nMOS transistor is under positive bias. Both the temperature effects decrease the transistor speed, in the long run, the system may fail due to timing violations. Usually consummation of a system depends on the throughput of the multiplier. So it is important to adopt a reliable high performance multiplier. The multiplier is able to attenuate the performance degradation due to aging. Improvement: Hence, the objective of the project is to design a high speed and power efficient multiplier to increase the performance of the device. Design of Multiplier circuit using Adaptive Hold Technique is proposed. By using AHT circuit we can reduce the NBTI andPositive Bias Temperature Instability(PBTI) effects, hence performance will be increased and the aging effects will be reduced. The proposed technique is done using Xilinx 14.7 tool. The code is simulated and synthesized and comparison results are made based on the performance of the multipliers with and without AHT.
Keywords: Aging, Attenuate, Hold Logic, Temperature Instability, Throughput


Subscribe now for latest articles and news.