Indian Journal of Science and Technology
DOI: 10.17485/ijst/2016/v9i44/105278
Year: 2016, Volume: 9, Issue: 44, Pages: 1-7
Original Article
Swapnil Sourav*, Rishab Mehra and Aminul Islam
Department of Electronics and Communication Engineering, Birla Institute of Technology (Deemed University), Mesra, Ranchi, Jharkhand – 835215, India; [email protected], [email protected], [email protected]
*Author for correspondence
Swapnil Sourav
Department of Electronics and Communication Engineering, Birla Institute of Technology (Deemed University), Mesra, Ranchi, Jharkhand – 835215, India;
Email: [email protected]
Objectives: The impact of process, voltage and temperature (PVT) variations on the voltage gain of a CMOS differential amplifier is investigated. Methods and analysis: Appropriate biasing is provided using diode-connected MOS voltage dividers. These dividers are less bulky as compared to their resistive counterparts, save chip area and provide better performance when subjected to variations. In addition, the transistors are sized suitably to minimize the effect of threshold voltage modulation in short-channel devices. Findings: The sensitivity parameters for the voltage gain are modeled and their dependences are studied. All simulation results have been performed using Virtuoso Analog Design Environment of Cadence @ 45-nm technology node. Application/ Improvement: Diode-connected MOS voltage dividers are used to bias the amplifier which provide immunity against PVT variations and hence improve system performance.
Keywords: Aspect Ratio, Differential, Gain, MOS Divider, Saturation, Sensitivity, Variability,
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