Simulation and Characterization of Junction Less CMOS Inverter at Various Technology Nodes

Vishal Narula; Charu Narula  and Jatinder Singh

doi:10.17485/ijst/2016/v9i47/106897

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Simulation and Characterization of Junction Less CMOS Inverter at Various Technology Nodes

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Indian Journal of Science and Technology

DOI: 10.17485/ijst/2016/v9i47/106897

Year: 2016, Volume: 9, Issue: 47, Pages: 1-7

Original Article

Simulation and Characterization of Junction Less CMOS Inverter at Various Technology Nodes

Vishal Narula¹ , Charu Narula² and Jatinder Singh²

¹Lovely Professional University, Phagwar -144411, Punjab, India; [email protected]co.in ²University Institute of Engineering Technology, Panjab University, Chandigarh – 160014, Punjab, India; [email protected], [email protected]

This work is licensed under a Creative Commons Attribution 4.0 International License.

Abstract

The simulation and drawing based on new type of technology namely junction less transistor technology CMOS inverter is discussed in this paper at various channel lengths. The transient curve, noise margin, various differences between conventional and junction less technology has been illustrated in this paper. The surface conduction and bulk conduction steps using visual TCAD is also expressed. The designing and fabrication steps along with the pros and cons have been characterized. The short channel parameter on which all other parameters directly or indirectly depends is calculated for both conventional and junction less transistor at different nodes. The noise margin and propagation delay at channel length 10nm, 20nm, 30nm and 40nm is calculated using TCAD simulation software. It has been found that CMOS inverter is giving best results when made using junction less technology.

Keywords: CMOS, Junction Less Transistor (JLT), Noise margin, TCAD