• P-ISSN 0974-6846 E-ISSN 0974-5645

Indian Journal of Science and Technology


Indian Journal of Science and Technology

Year: 2016, Volume: 9, Issue: 12, Pages: 1-8

Original Article

Survey on Energy - Efficient Methodologies and Architectures of Network-on-Chip


The emergingtechnology requiresa large number of core to be integrated into a single chip.This had led to the development of System on Chip. SoC’shave paved way for large scale integration of electronics mounted on a single chip. SoC’s are nowadays highly preferred for designing portable and compact devices with low power. The complex and complete integration of SoC has paved way for the concept of Network on Chip (NoC). NoC is a key challenge for power optimization as they are battery operated. In this paper survey provides a design of energy aware NoC with reduced power consumption and enhanced performance. A broad view of power optimization using voltage/frequency Island is provided. The paper also provides a detailed survey of the different data encoding techniques and their efficiency. The objective of this survey is to provide information regarding improved design for reducing power in NoCs. The survey also helps to arrive at a conclusion of the various power optimization techniques.

Keywords: Data Encoding Techniques, Network on Chip, System on Chip, Voltage/Frequency Island. 


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