Indian Journal of Science and Technology
Year: 2016, Volume: 9, Issue: 36, Pages: 1-7
S. Malarvizhi*, Rakshaka Ramu and J. Manjula
1 Electronics and Communication Department, SRM University, Kattankulathur, Chennai - 603203, Tamil Nadu, India; [email protected]
*Author for correspondence
Electronics and Communication Department
Email: [email protected]
Objectives: In this paper, the authors perform the physical design flow of Microprocessor without Interlocked Pipelined Stage MIPS, which is register based architecture in detail which aims to minimize IR drop in pre-circuit stage. The intent of this work is to analyze the IR drop and to make sure that the power supply is delivered across the entire chip. Technology shrinking makes it difficult to deliver complete supplied voltage to all the placed standard cells. And it becomes difficult to meet the slack time. The placement algorithm has also been proposed in the work. Methods/Statistical Analysis: The switching activity of the clock signal dynamically varies the IR drop at each buffer. Hence, depending on the level of IR drop, the current delivered by the buffers will be varied. This has led to the fluctuation of the supply voltage, which in turn causes variations in the delay, skew and slew rates. These effects necessitate the detailed timing analysis of the circuit. It can be observed that 10% IR drop causes an increase in delay of about 5% to 10%. Findings: The Register Transistor Level of MIPS design has been converted into net-list using Cadence Encounter RTL Compiler. The net-list is imported in Encounter GDSII for the Physical Designing. The Cadence Encounter Digital Implementation (EDI) used in the paper is 90 nm technology. The floor plan results of the design shows that the cells utilization is 70% and rest of the 30% is left for routing the design. The fly-line analysis is done in floor-planning stage to estimate the placement of the logic cells. The core utilization is 69% while the distance between the core and die is10 µm. The circuit is operated with the supply voltage 1.628 V and the IR drop analysis has been performed to all the standard cells in the design. The design also meets Slack time, Setup time, Hold time. Thus the Timing Aware IR drop has been analyzed in the paper. The MIPS design operates at 100 MHz Frequency. The MIPS design shows an appreciable decrease in the turnaround time which is 2.38 ns. Application/Improvements: The physical design of MIPS gives better IR drop and turnaround time. Power consumption in pre-placement, post-placement of the design is reported to be 11.37 mW and 11.77 mW.
Keywords: Cadence Encounter, IR Drop Analysis, MIPS, Physical Design
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