Indian Journal of Science and Technology

Abstract

Background/Objectives: Dynamic Power reduction has become a very important issue in the design of System on Chip (SOC). One of the methods for reduction is use of multiple supply voltage (MSV). In this MSV design, the modules are placed in the contiguous region such that modules of same operating voltage are placed in a same region. Such regions are called as Voltage Island. In this process, voltage assignment is followed by floor planning to avoid geometric constraints and physical information of the design. But increase in number of voltage island causes increase in number of level shifters between voltage islands. In this paper, we consider the Intellectual Property (IP) core based Voltage Island driven floorplanning problem including voltage island reduction. Voltage island reduction is carried over by matching algorithm. Methods/ Statistical Analysis: The proposed matching algorithm constructs a graph G consisting of vertices as Voltages Island and edges as connectivity between Voltage Islands. The proposed matching algorithm takes care of number of modules and interconnects in between Voltage Island while contracting the vertices. Findings: The result of proposed matching algorithm is taken as candidate solution represented by Sequence Pair technique, for floorplanning. A new genetic algorithm based optimization is proposed to give the best solution of floorplan which reduces the dynamic power. The proposed algorithms are compared with two approaches such as partitioning the modules on the critical path and partitioning the modules of same operating voltage. Experimental results show that our proposed algorithm for voltage Island reduction and floorplanning minimizes the number of level shifters and overall Dynamic Power of circuit. Applications/Improvements: The proposed algorithm plays a significant role in the developing CAD software for the SOC Design. Our future work is on developing a suitable data structure for the floorplanning for multiple voltage design which includes IR drop in power rails as constraint. We also planned to focus this issue of multiple voltage design towards 3D ICs.
Keywords: Floorplanning, System on Chip, VLSI, Voltage Assignment