Indian Journal of Science and Technology
Year: 2017, Volume: 10, Issue: 14, Pages: 1-7
M. Senthil Kumar* and G. V. R. L. Maccalay
*Author for correspondence
M. Senthil KumarElectronics and Communication Engineering, Tirumala Engineering College, Hyderabad – 501301, Telangana, India; [email protected]
Objectives: AES(Advanced Encryption Standard) provides strong encrypted information and also it is easy to produce on a miniature die size and consume low power by reducing the number of gates and transistors in the S-box of AES. The main aim of project is to reduce the number of gates in AES S-box to achieve low area and low power. Methods/Analysis: The proposed technique uses the logical level reduction technique to achieve less number of gates by using Boolean logic. The target of the proposed technique is to design the compact multiplicative inverse unit by circuit and gate level implementation in order to achieve low area and low power utilization. The structure of multiplicative inverse unit is reduced by using logical simplification. The simulation is performed by Tanner tool version 14.11 for circuit level implementation based on static complementary metal oxide semiconductor (CMOS) logic. This tool also provides the information about number of transistors utilized and power consumption of both existing and proposed multiplicative inverse unit. Findings/Novelty: Several cryptographic techniques such as Data Encryption Standard (DES), AES(Advanced Encryption Standard), blowfish and RC4 are adopted based on various applications for specific purposes. Among various techniques, AES provides high security with low power and low area utilization. The conventional multiplicative inverse (MI) unit of AES has 50 gates to perform the multiplicative inverse (MI) operation. So it needs more area and power. To overcome this problem, Boolean logic is applied to perform the logical simplification of the proposed multiplicative inverse unit. From that, it reduces from 50 gates to 39 gates than the existing Mt unit. Totally, 11 gates are reduced in the proposed multiplicative inverse unit. Always the area is directly proportional to the power consumption. The power consumption of the proposed circuit is reduced from 45.7mw to 36.7mw.The proposed multiplicative inverse unit offers 22% area reduction and 19.6% power reduction than the existing MI unit. Applications/Improvement: In the proposed multiplicative inverse unit, only 4 XOR gates are used instead of 14 XOR gates to perform the operation and this in turn helps to achieve less area and low power. The proposed multiplicative inverse unit based AES is applied for low area and low power with high security applications.
Keywords: AES, Galois Field Arithmetic, Reduced MI Unit, S-Box, Static CMOS and Boolean Logic
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