Indian Journal of Science and Technology
Year: 2012, Volume: 5, Issue: 10, Pages: 1-6
Mahdi Koohi1 , Hassan Bayadi2 and Mansour Nourmohamad Khaless3
1 Department of Electrical Engineering,
2 Department I.E Engineering Sience&Technology,
3 Department of electrical engineering,[email protected]; [email protected]; [email protected]
Abstract This study is centered on the architectural efficacy of network processors based on simultaneous multi thread (SMT) architecture that support multiple active concurrent hardware threads at the same time with the goal of sharing processor resources such as functional units and memory. This thread-level-parallelism can be exploited in packet processing devices called network processors. The programs running on network processors have different characteristics depending on where the processor is used and the input workload. In this paper , we introduce our simulation environment, called SNP (Simulator for Network Processor), for simulating a typical SMT network processor which includes a connected network controller and a packet generator. The simulator presented in this study is a process based “simulator for Network processor” (SNP) usable for different modes and applications based on “clock – by – clock” method and is described according to SMT Structure. The simulator architecture is performed by C++ language optimized as efficient as possible. Such simulator is similar with simple scalar simulator.
Keywords: Network Processor, Router, Packet, Simulator, architectural efficacy
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