Indian Journal of Science and Technology
Year: 2018, Volume: 11, Issue: 19, Pages: 1-6
S. Tamilselvan and A. Arun
*Author for correspondence
Department of Electronics and Communication Engineering, M. Kumarasamy College of Engineering, Karur - 639113, Tamil Nadu, India; [email protected]
Objectives: An efficient MAC design is planned for 2’s complement numbers with no more than partial-product creation methodology and diminution tree, whereas the succeeding step trappings an extraordinary sign-conservatory solutions. Methods/Statistical Analysis: Accumulate operations form an important process in signal and image processing applications. To expand MAC execution, the basic way postponement can be diminished by embeddings an additional pipeline register, either in the interior the two rows or stuck between the twos and the final adder. Findings: The 16 bit MAC architecture is implemented using Baugh-Wooley (BW) multiplier with Twin precision concept. The proposed methodology is verified by implementing in a 16 x 16 MAC unit. The performance parameters extracted demonstrates that the proposed Modified Booth with Twin precision based 16 bit MAC demonstrates an area reduction of 45.3%, delay reduction of 30.8% and power saving of 60% when compared to the MAC architectures designed using Baugh-Wooley with twin precision multiplier. Application/Improvements: It performs better than the conventional MAC in all the aspects.
Keywords: Baugh-Wooley Multiplier, MAC Design, Partial-Product, Sign-Conservatory Solutions, Twin Precision
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